A pre-registered junction-invention benchmark under BIT-OS/CIP v1. 2. A boundary-surprise gate (|ΔArea|>θ) augmented with geometric confirmation (two ~½-area daughters + midpoint symmetry) cuts false-split rate ~90% and lifts selectivity Rₛel 0. 29→2. 15. The case nonetheless fails its pre-registered system pass-rule: the locked aggregate metric is dominated (84%) by steady-state ID-switch, capping any division handler at ~15% and actively de-prioritizing division recall under tuning. Published as a first-class negative result with full harness and per-arm-per-seed receipts. Synthetic data only; no novelty claim (prior-art search pending).
Bùi Quang Trịnh (Mon,) studied this question.
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