What question did this study set out to answer?

The research aims to create a more efficient LDPC decoding architecture that minimizes hardware and memory usage while enhancing error correction.

February 2, 2026Open Access

Reduced Check Node Storage for Hardware-Efficient LDPC Decoder

Key Points

The research aims to create a more efficient LDPC decoding architecture that minimizes hardware and memory usage while enhancing error correction.
Developed a Variable Single minimum Min-Sum algorithm for efficient check node processing.
Implemented a memory splitting strategy to optimize memory use based on LDPC code properties.
Demonstrated performance using a Xilinx Kintex UltraScale+ FPGA.
Achieved over 46.2% reduction in storage requirements compared to conventional decoders.
Improved performance by up to 0.38 dB at a Bit Error Rate (BER) of 10⁻⁸.
Outperformed traditional Min-Sum-based decoding approaches.

Abstract

This paper proposes a hardware- and memory-efficient architecture for Low-Density Parity-Check (LDPC) decoding, targeting enhanced-performance applications with constrained resources. The design integrates two novel techniques: (i) the Variable Single minimum Min-Sum (VSMS) algorithm, which reduces hardware complexity by identifying the first minimum value and its position during check node processing, while improving error correction through a correction factor applied in variable node updates; and (ii) a memory splitting strategy that exploits the structural properties of LDPC codes to optimize memory usage. Implementation on a Xilinx Kintex UltraScale+ (xcku5p) FPGA demonstrates a reduction in storage requirements by over 46.2% compared to conventional decoders. Furthermore, the proposed decoder achieves a performance gain of up to 0.38 dB at a Bit Error Rate (BER) of 10⁻⁸, outperforming traditional Min-Sum-based approaches.

Reduced Check Node Storage for Hardware-Efficient LDPC Decoder

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Abstract

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