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Recognizing the simplified fabrication and advanced performance of Vertical Tunnel Field Effect Transistors (VTFET) compared to Lateral TFET, numerous research has been con-ducted. In this study, a comparative analysis was performed on two double gate heterojunction source-pocket engineered VTFETs with and without heterogeneous cascaded gate dielectric using ATLAS SILVACO TCAD software. Highly doped GaSb as source intensifies the tunneling rate. GaAs₀. ₅ Sb 0. 5 as source pocket reduces lattice mismatch and increases I₎₍. The research indicates that using High-k and & Low-k thick gate dielectrics at source and drain ends reduces average subthreshold swing (SS₀ₕ₆), enhances transcenductance (g₌), and amplifies I₎₍/I₎₅₅ ratio exponentially. This research examines Analo yₑ₅ and DC performances of VTFET to optimize crucial device parameters. The heterogeneous gate dielectric structure incorporating HfO₂ showed an improved I₎₍ of 1. 1 10^-5A/ m, diminished leakage current I₎₅₅ of 1. 05 10^-17A/ m, SS₀ₕ₆ of 19. 6 mV/dec, highest I₎₍/I₎₅₅ ratio of 1. 04 10^12 and g₍₋ of 45 S. The analysis revealed that the study is appropriate for assessing low-power applications with increased performance and also has a great potential for broadening the realm of vertical TFETs.
Mahbub et al. (Thu,) studied this question.
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