Exploiting HPC Techniques to Parallelise Simulation of 10B+ Transistor SoCs

TL simulation has become a crucial bottleneck in the design of emerging SoCs for AI. To clear this bottleneck, design teams are leaning ever more heavily on emulation and other alternative tools. We find that the designer can instead exploit the natural boundaries of these emerging SoCs in order to parallelise their RTL simulations using HPC techniques. By distributing Verilog simulation across tens of HPC nodes (and thousands of physical cores), we can simulate a 10B+ transistor, 1024 core SoC with over 2.7MIPS of aggregate throughput for the simulated cores. This talk will describe the insight, HPC techniques, and efficiency results of our novel open-source approach, known as Metro-MPI.