This paper presents a systematic design of a low-flicker-noise LC voltage-controlled oscillator (VCO) and its application in a jitter cleaner phase-locked loop (PLL). In the LC VCO design, the 1/f 3 corner frequency is reduced from 1 MHz to below 100 kHz through the coordinated optimization of a multilayer inductor, tail resistor biasing, and supply voltage. This optimization suppresses the upconverted flicker noise and significantly reduces the integrated RMS jitter, which is critical for ultra-narrow bandwidth PLLs. The inductor design employs a stacked structure to achieve higher selfresonant frequency and stable inductance. For the active core, long-channel transistors are utilized to minimize flicker noise injection. At the tail, resistor degeneration replaces the conventional current source, effectively lowering flicker noise while maintaining robustness against process, voltage and temperature (PVT) variations. The capacitor array features a switching topology with varactors ratioed to the main varactor, complemented by a MOSFET-C low-pass filter on the control lines to suppress driver-stage noise, reducing flicker noise contribution by 30% while ensuring tuning linearity. To suppress the jitter peaking effect, a large off-chip capacitor is used for the loop filter, resolving the area-versus-parasitic trade-off of on-chip solutions and enabling an overdamped design that reduces jitter peaking to below 0.2 dB. Furthermore, a fast-locking mechanism is introduced to overcome the long settling time associated with the narrow-bandwidth, with experimental results showing nearly 90% reduction in lock time. Post-layout simulations in 110-nm CMOS process show that the design occupies a core area of 0.69 mm 2 , achieves a 2.97 GHz output with integrated jitter of 0.9 ps and phase noise below -120 dBc/Hz at 1 MHz offset, meeting SMPTE 425 standard requirements.
Meng et al. (Wed,) studied this question.