What question did this study set out to answer?

To develop a low-flicker-noise LC VCO suitable for use in a jitter cleaner PLL that minimizes RMS jitter and reduces lock time.

A Jitter Cleaner PLL with Low 1/f ³ Noise LC VCO and Fast-Locking Aids in 110nm CMOS

View Full Paper

Ask AI

Bookmark

To develop a low-flicker-noise LC VCO suitable for use in a jitter cleaner PLL that minimizes RMS jitter and reduces lock time.
Systematic design of a low-flicker-noise LC VCO
Optimization of multilayer inductor, tail resistor biasing, and supply voltage
Utilization of long-channel transistors to minimize flicker noise
Implementation of a switching topology in the capacitor array
Introduction of a fast-locking mechanism to enhance settling time
Reduced 1/f 3 corner frequency from 1 MHz to below 100 kHz
Achieved integrated RMS jitter of 0.9 ps and phase noise below -120 dBc/Hz at 1 MHz offset
Reduced the jitter peaking effect to below 0.2 dB
Nearly 90% reduction in lock time
Design occupies a core area of 0.69 mm² with a 2.97 GHz output

No takes yet. Share an insight, caveat, or question.

This design optimizes a low-flicker-noise LC VCO for a jitter cleaner PLL, reducing lock time in high-performance circuits.

Meng et al. (2026) studied this question.

View Full Paper

Ask AI

Bookmark