Design and Implementation of a Single-Bit Fault Detecting Reversible Arithmetic Logic Unit Using Fredkin and CNOT Gates

Reduction in dimensions of CMOS technology has resulted in great increase in computing speeds but, at the same time, higher power consumption. Thus, a serious limitation arises since conventional approaches will eventually hit the physical limit 1, 2. Reversible computing seems promising in the context of VLSI. In theory, it could operate without any energy loss due to lossless information processing 3, 4. The paper presents development and implementation of a reversible Arithmetic Logic Unit (ALU) based on quantum logic gates working with qubits. The architecture is based on Fredkin gates (quantum cost 5) and CNOT gates (quantum cost 1), both preserving parity and being inherently reversible. The ALU can execute all arithmetic and logical operations and reconfigure operations dynamically according to system requirements. Also, the designed ALU possesses an inherent parity-preserving fault detection mechanism for reliable identification of single-bit faults. Overall the implemented ALU contains 9 CNOT and 7 Fredkin gates resulting in quantum cost equal to 44 and 12 garbage outputs. Thus, the quantum cost and garbage outputs are significantly lower than usual ones for the design of a reversible ALU, which generally amount to 48–65 and 16–20 correspondingly. The designed architecture is described in details through the application of Verilog HDL and simulation in Xilinx Vivado toolset. The work concentrates on optimization of such important parameters as the number of gates, quantum cost, garbage outputs, and constant inputs. Those design parameters are critical in order to develop scalable and sustainable quantum and low-power VLSI architectures.