Non-Fourier thermal analysis of the self-heating effect in CMOS logic circuits

Accurate thermal analysis is essential for modern integrated circuit design. This becomes particularly critical as semiconductor process technology advances into the post-Moore era, where non-Fourier effects dominate thermal transport in nanoscale transistors. Conventional circuit-level thermal analysis primarily relies on thermal compact models and the equivalent thermal resistance (RC) network. However, these methods are based on the heat diffusion equation, failing to accurately capture non-Fourier effects and thermal coupling effects between cells in circuits. In this work, we develop the phonon Boltzmann Transport Equation (BTE)-based framework for transient thermal analysis of standard CMOS logic circuits with advanced technology nodes, enabling a comprehensive consideration of non-Fourier effects and thermal coupling effects. Using the inverter cell as a demonstration, we investigate the transient self-heating effect (SHE) under varying slew-load combinations and derive a temperature-power model based on the non-gray phonon BTE. Our results demonstrate that SHE can lead to a 2.3% reduction in noise margin and a 9.2% increase in the propagation delay of the inverter, thereby posing a considerable threat to circuit functionality. Furthermore, the mixed-mode simulation is applied to analyze the electrothermal behavior of multi-stage ring oscillators to demonstrate the scalability of our approach to larger circuits. This work provides a precise demonstration of the thermal behavior of logic circuits and thermal-aware reliability challenges in both transistors and circuits, providing valuable insights for optimizing integrated circuit design and thermal management.