On the Severity of Self-Heating in FDSOI at Cryogenic Temperatures: In-depth Analysis from Transistors to Full Processor

Cryogenic CMOS devices face the challenge of excessive self-heating (SH), which has emerged as a major concern for quantum computing (QC). This work is the first to reveal the impact of SH in cryogenic circuits, from the transistor level all the way up to the processor level, using the 28nm FDSOI technology. The heat generated from cryogenic interfacing circuits severely hinders the lifetime of qubits, which are thermal noise-sensitive. To investigate the impact of SH on cryogenic circuits, we first extend the industry-standard BSIM-IMG model to incorporate the physics-based cryogenic temperature-specific transistor characteristics and then validate our model against measured data. Then, the calibrated transistor models are employed to create novel cryogenic-aware and SH-aware standard cell libraries. We deploy those libraries within industrial EDA tools, such as logic synthesis and timing signoff, to unveil the overall impact of SH on various complex circuits, including a full RISC-V processor core.