Design of BPC LF Time Code Signal Generator Based on ARM Architecture Microcontroller and FPGA

Low-frequency (LF) time code timing technology holds significant importance in civilian applications such as radio-controlled clocks. This study focuses on the design and implementation of a high-precision Binary Phase Code (BPC) LF time code signal generator. A generator system was constructed, demonstrating good stability, superior resolution, and flexible adjustment capabilities for both amplitude and phase. The system employs an ARM + FPGA cooperative architecture: the ARM processor is responsible for parsing and scheduling the time code data, while the FPGA implements carrier wave generation and high-precision digital modulation. This digital processing is combined with analog circuitry to achieve digital-to-analog (D/A) signal conversion. Compared to traditional methods, carrier generation is achieved using Direct Digital Synthesis (DDS) technology. Digital modulation techniques enable the precise control of the modulation depth (adjustable between 70% and 90%) and phase (with a resolution of 1 ns). A sliding window algorithm was utilized for time difference calculation and compensation. Testing confirmed the stability of key signal parameters, including integrity, carrier frequency and modulation depth. These results validate the feasibility and superiority of the digital LF time code generation technology proposed in this study, providing a valuable reference for the development of next-generation timing equipment.