Defect-Aware Extreme Device Scaling Limits of 2D Memristive Technologies

Abstract Memristors hold great promise for next-generation artificial intelligence hardware, however, this requires their extreme miniaturization for high-density crossbar arrays. The challenge lies in that conventional memristor operation depends on defects that have stochastic geometric distributions and stochastic electrical properties. Characterizing stochasticity at extreme device scaling limits, where its impact becomes most prominent, poses challenges for systematic design and comprehensive analysis. Here we present a systematic bottom-up characterization framework that predicts and analyses the impact of stochastic atomic defects on wafer-scale memristor performance at extreme device scaling limits. The framework couples state-of-the-art experimental characterization with novel atomic stochastic geometry modelling, providing insights into device yield, performance, and variability. This defect-aware framework reveals that vertical filamentary-type 2D memristors (h-BN based) can attain high device yield ( > 99.999 %) at extreme miniaturization limits; however, device performance and device-to-device variability are adversely affected, due to the increasing impact of weak defects at these limits. Therefore, our analysis suggests that extremely-scaled filamentary-type memristors may be more suited to applications that leverage stochasticity, such as encryption and probabilistic computing, whose design can be guided using our framework.