Deterministic Switching‐Path Engineering of CMOS‐Integrated 2D Memristors for Neuromorphic Computing

Two‐dimensional (2D) memristors are promising for low‐power and high‐speed neuromorphic hardware. However, their performance under circuit‐level constraints remains limited because resistive switching relies on native defects, hindering precise control of filament formation. Here, we report 2D MoTe 2 memristors that integrate deterministic switching‐path density engineering with CMOS‐compatible one‐transistor‐one‐memristor (1T‐1 M) architectures. The devices exhibit highly linear and symmetric synaptic plasticity (α p /α d = 0.019/0.2), enabled by a balanced interplay between filament formation and confinement. Furthermore, monolithic integration with silicon transistors enables gate‐tunable compliance control, which suppresses variability and stabilizes array‐level operation. The resulting 1T‐1 M arrays exhibit a wide dynamic range (∼22×), and minimal potentiation/depression variation (7.95%/6.22%). Device‐aware simulations based on multilayer perception, convolutional neural network, and autoencoder models confirm improved learning accuracy compared to passive arrays. This work establishes a materials‐to‐circuit design framework that links defect‐path engineering with transistor‐assisted current control, providing a practical pathway toward 2D neuromorphic hardware.