Novel approach reduces spurious frequencies in digital DAC applications, highlighting efficiency through modeling simulations.
In this paper, we present a novel first-order digital ΣΔ converter tailored for digital-to-analog applications, focusing on achieving both high yield and reduced silicon estate. Our approach incorporates a substantial level of dithering noise into the input signal, strategically aimed at mitigating the spurious frequencies commonly encountered in such converters. Validation of our design is performed through simulations using a high-level simulator specialized in mixed-signal circuit analysis. The results underscore the enhanced performance of our circuit, especially in reducing spurious frequencies, highlighting its efficiency and effectiveness. The final circuit exhibits an effective number of bits of 13.
No takes yet. Share an insight, caveat, or question.
Leduc et al. (2025) studied this question.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: