In this paper, a new method for multistage digital sigma–delta modulators (DDSMs) is presented to increase the output sequence period and reduce fractional spurs. The output of a DDSM is always a periodic signal when the input is constant. A hybrid DDSM is premiere to its conventional counterpart for having a potential speed, by the choice of its smaller bus. In this paper, the spurious tone periodicity is maximized by combining the dither method and the deterministic method. In the proposed third‐order sigma–delta modulator, zero‐order and first‐order shaped dither can be used to reduce fractional spurs and increase the periodicity. Design results confirm the theoretical predictions. In addition, the results of circuit implementation proposed method reports and the power consumption of this proposed structure for different transistor models. In this paper, a third‐stage modulator with pseudorandom dither is presented, which has lower hardware and power consumption than other methods. This modulator is simulated at the transistor level, and the current and power consumption of the modulator are calculated. New features in the proposed work include using an alternating dither signal for alternating mode changes of the modulator input, using a third‐order modulator with a discrete line method to reduce hardware consumption, and implementing the proposed modulator at the transistor level. When designing a circuit, implementing transistors, simulating various circuits, and calculating their dynamic power consumption have been one of the major challenges.
Sadatnoori et al. (Thu,) studied this question.