Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDR

This paper presents the non-idealities analysis, modelling and circuit implementation of a second-order two-bit Continuous-Time (CT) Sigma-Delta Modulator (SDM). The non-idealities such as quantizer metastability, clock jitter, finite integrator DC gain, circuit noises and non-linearities are discussed. Discrete time (DT) SDM model is first developed and then mapped onto CT-SDM model. Finally the circuit is implemented in 130 nm CMOS technology. It achieves a simulated 53.6 dB DR and 51.4 dB SNDR over a 20MHz signal bandwidth. The sampling clock frequency is 640 MHz, producing an Over-Sampling-Ratio (OSR) of 16. Second order loop is intrinsically stable, while higher order loops tend to be unstable and much effort must be taken to maintain stability. Multi-bit internal quantizer is employed to obtain more aggressive quantization noise suppression and lower clock jitter sensitivity compared with higher order single bit structure. Spectre simulation shows that the power dissipation of the circuit is about 6 mW at 1.8 V supply.