Optimization of ZnO thickness for high-performance thin-film transistors and their application in 2T0C DRAM memory cells

Zinc oxide (ZnO) thin-film transistors (TFTs) have garnered significant attention in recent years due to their high field-effect mobility (μ FE ), low power consumption, and excellent optical transparency, making them promising candidates for applications in displays, sensors, and memory devices. The thickness of the ZnO active layer plays a critical role in determining key device parameters, including threshold voltage (V th ), field-effect mobility (μ FE FE ), subthreshold swing (SS), and current on/off ratio (I ON /I OFF ). However, a comprehensive understanding of the correlation between ZnO thin-film thickness and TFT performance, particularly in terms of electrical stability and memory applications, remains limited. To bridge this gap, this study systematically investigates the influence of ZnO thin-film thickness (14–20 nm) on TFT performance and explores its feasibility in a capacitorless 2T0C DRAM architecture. The findings provide valuable theoretical insights and experimental validation for optimizing ZnO TFTs for next-generation memory applications.