Memory Access Priority Circuit Design and Veri cation in Heterogeneous Multi-core Systems

Abstract As heterogeneous multi-core systems become more prevalent in fields such as autonomous driving, deep learning, and edge computing, the memory access requirements of these cores differ significantly. These differences lead to frequent bus contention and thread interference issues, which limit system performance improvements. To address these challenges, this paper focuses on designing a memory access optimization for heterogeneous multicore systems and proposes a modular memory controller architecture based on the AXI bus protocol. This architecture resolves memory access conflicts among heterogeneous cores effectively by integrating a hierarchical port arbitration mechanism with a dynamic command priority scheduling strategy. To validate the solution's effectiveness, we conducted functional verification and performance testing using the UVM verification platform. The experimental data show that the proposed controller improves memory access efficiency by 13.51% compared to the prototype controller in a heterogeneous multicore system environment, clearly highlighting its potential for practical engineering applications.