FPGA-Based Softcore Multiplier Design based on Look-up Table Encoding

This work presents an efficient softcore multiplier for Xilinx (now AMD) Field Programmable Gate Arrays (FPGAs). The indispensability of multiplication operations in Digital Signal Processing (DSP) applications is well established. Evidently, FPGA vendors include high-performance hardwired and softcore multipliers as part of their offerings. Hardwired multipliers are based on DSP blocks and are typically limited in number. Further, they suffer from high interconnect delays when used in some applications due to their fixed position. Softcore IP multipliers are flexible and offer the best performance in both standalone and embedded applications. In this work, we present the design of a softcore multiplier that outperforms the state-of-the-art Xilinx softcore IP multiplier (12.0). Our design is based on the efficient translation of the multiplier Boolean network into a circuit netlist that can be optimally mapped onto the inherent FPGA fabric. Implementation on Virtex-7 xc7vx330t FPGA device reveals an improvement of 31% and 33% in Lookup Table (LUT) count and Critical Path Delay (CPD) when compared to area-optimized 8-bit unsigned IP multiplier (12.0). For the speed-optimized IP multiplier (12.0), our design shows an improvement of 41% and 19% in LUT count and CPD, respectively.