Modified Spike Backpropagation Design towards Highly Parallelable Hardware Implementation

Abstract This work presents a hardware-algorithm co-designed framework for neuromor-phic computing, enabling efficient supervised learning in spike-based neural architectures. First, synaptic updates are reformulated as low-rank outer products of forward spike vectors and backward error gradients via singular value decomposition (SVD), enabling direct parallelization on 1T1R arrays. Second, a stochastic computing scheme replaces conventional sequential updates with probabilistic pulse-driven modulation, achieving one-step full-matrix synaptic updates. Third, gradient stabilization techniques mitigate training instability in deep SNNs by addressing silent neuron and gradient explosion issues. 1 Evaluated on the ASL-DVS dynamic gesture recognition task, the framework maintains 84.7% accuracy with hardware-realistic 1T1R characteristics, while drastically reducing hardware update steps. This demonstrates a syner-gistic hardware-algorithm co-design where SVD-based approximation enables parallelization, stochastic computing achieves one-step updates, and gradient stabilization ensures trainability, advancing practical neuromorphic intelligence for edge sensing systems.