P‐224: Late‐News Poster: Interfacial Oxidation Layer for Reliable Vertical Thin‐Film Transistors

A new fabrication method for vertical thin‐film transistors has been developed, where traditional spacers are replaced with gate metals and interlayer dielectrics are substituted with interfacial oxide layers. This approach simplifies the manufacturing process while forming distinct interfacial oxide layers at the upper and lower regions of the vertical thin‐film transistor structure. Previous experimental results indicated a significant difference in breakdown voltage between the upper and lower interfacial oxide layers, with the lower layer demonstrating superior electrical performance under applied voltage. For a more thorough analysis, three different structures were analyzed to evaluate the detailed characteristics of the interfacial oxide layers. The analysis included variations in annealing temperature and time. Additionally, the overlap region between the Indium Tin Oxide and gate metal was examined to identify the thickness distribution. A comprehensive evaluation was conducted, encompassing thickness measurements, structural analysis, breakdown voltage assessments, and compositional analysis. The experimental results demonstrated an optimal interfacial oxide thickness, stable breakdown voltage, and favorable compositional properties, making it well‐suited for low‐voltage operation. These findings validate the potential of interfacial oxidation as an effective gate insulator, paving the way for simplified, scalable, and cost‐effective vertical thin‐film transistor fabrication processes for next‐generation electronic devices.