Efficient Implementation of a Balanced Dynamic TDMA Arbitration Scheme for System-on-Chip Buses

This paper proposes a balanced dynamic Time Division Multiple Access bus architecture with a novel selectable–sequence–counter arbitration circuit. Most existing dTDMA-related studies focus on wireless communications, which involve significantly different architectural assumptions, design constraints, and implementation platforms compared to digital bus systems. Our comparative analysis was carried out against the only available implementation in the literature, aligning to the target domain of digital buses. The proposed SSC-based arbiter, evaluated on a 65 nm CMOS process, demonstrates superior performance, achieving substantial reductions in area and power consumption with an approximated linear resource scaling as the number of connected devices to the bus increases, unlike the quadratic growth in the conventional architecture. Thus, this work offers a practical and yet efficient novel dTDMA architecture solution for on-chip communication.