Three Level Pulses to Investigate Gate Switching Instability

We use novel three-level pulse sequences, where the intermediate level is either above or below the threshold voltage, to investigate gate switching instability (GSI) in 4H-SiC-MOSFETs. Results with sequences with an intermediate level above the threshold voltage ( V th ) seem to falsify the hypothesis that trapped holes remaining at the interface after switching to the on-state, are the root cause for GSI, as was described in [1, 2]. Fast switching applications may cause negative transient pulses on the gate electrode during the off-state. Results with sequences with an intermediate level below threshold show that such transients may cause an increased V th -drift. Introducing a delay between the transient and the turn-on of the transistor in such pulse sequences, does not mitigate the effect of a negative transient on the V th -drift.