SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

There are some technological issues in SiC MOSFETs that are still unsolved. One of the main problems is the high density of traps/defects at the SiC/SiO 2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. The high-density of defects at the SiC/SiO 2 interface is a relevant problem since it can influence the overall performance of the device, causing detrimental impacts on threshold voltage stability, channel mobility and leakage current amplitude. Due to the fundamental importance of the SiC/SiO 2 interface characterization, several techniques have been employed to investigate defects properties related to this region. In this work non-classical C-V measurements are performed. Capacitance is measured between Gate and Source terminals while a fix DC voltage is imposed on the Drain. This latter is considered among positive values in the first case, while it is chosen as a negative voltage in the second case. The arising capacitances in both cases show an unexpected behavior which can be related to interface properties. To this aim numerical analysis is performed in Sentaurus TCAD environment.