Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

The effects of positive and negative high voltage gate stress on the interface trap density and channel conductivity of lateral, Si-face 4H-SiC MOSFETs is studied, and the possible physical mechanisms for interface trap generation are discussed. Charge pumping and I D -V GS measurements are used to measure the trap density and field-effect mobility, respectively. The time dependence of the channel degradation is evaluated for different stress voltages with oxide electric field exceeding 8 MV/cm. Positive stress is shown to generate acceptor traps which degrade the field-effect mobility, and the density of traps follows a universal dependence on the injected electron fluence into the gate oxide. In contrast, negative stress resulted in no degradation of the field-effect mobility even as interface trap density increased, indicating that only donor interface traps are created. Furthermore, the trap density during negative stress does not follow a universal dependence on the injected hole fluence, indicating that other mechanisms are responsible for the trap creation.