Hole-Induced Threshold Voltage Instability Under High Positive and Negative Gate Stress in SiC MOSFETs

This study investigates hole-induced threshold voltage instability at high positive and negative gate stress in n-channel 4H-SiC power MOSFETs. Irrespective of the origin of the holes, whether it is from bandgap impact ionization in SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> under high positive gate bias or from the Fowler-Nordheim tunneling under high negative bias, the threshold voltage (VT) is observed to decrease due to the accumulated fixed charge when holes fill existing oxide hole traps. Our study addresses this phenomenon of VT decrease, and the subsequent restoration of VT by the virtue of counterbalancing phenomenon such as electron-hole recombination or hole de-trapping to increase VT at positive gate bias. Therefore, threshold stability should be considered when any bias well above the recommended maximum use bias is applied.