Design of High-Performance,ultra-Low Power Level Shifter for Digital Cmos Circuits

This paper presents the design and simulation of an ultra-low leakage, wide-range voltage level shifter optimized for low-power digital CMOS VLSI applications. Implemented in 45 nm technology, the proposed circuit efficiently converts low-voltage input signals (0.3V) to a higher output voltage (1.2V) while minimizing power dissipation. The design incorporates leakage shut-off transistors and a low-threshold pulldown network to enhance energy efficiency and transition speed. Simulation results demonstrate a static power consumption as low as 140 fW in the Fast-Fast (FF) process corner and up to 180 fW in the Slow-Slow (SS) corner. The level shifter achieves a propagation delay between 5.8 ns (FF) and 8.5 ns (SS), with energy per transition ranging from 0.81 fJ to 1.53 fJ. These results validate the circuit’s robustness and efficiency across different PVT variations, making it a suitable design for ultra-low power.