Introduces a novel high-voltage level shifter that improves performance in DC–DC buck converters, indicating potential for more efficient power management.
This paper introduces a level shifter designed for high-voltage DC–DC buck converters. Compared with the conventional level shifter, the proposed level shifter incorporates a novel digital control scheme that actively selects the output signal that first meets the logic threshold, whether rising or falling, thereby significantly enhancing both propagation delay and delay matching. Furthermore, enhanced noise immunity is achieved by the clamping isolation MOSFETs during high dV/dt transitions. Implemented in a 0.18 μm BCD process, post-layout simulation results indicate a propagation delay of 0.58 ns, a worst-case delay mismatch of 0.07 ns, and a dV/dt immunity of 350 V/ns.
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Yu et al. (2026) studied this question.
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