A lightweight fault diagnosis network based on FPGA and feature knowledge distillation

Although deep learning has shown great promise in fault diagnosis tasks, the deployment of high-performance models typically relies on graphics processing units (GPUs) or powerful workstations, resulting in increased power consumption and cost. These constraints hinder their practical application in real-world industrial environments. This paper presents a high-efficiency fault diagnosis network employing feature-level knowledge distillation, which is implemented on a low-power embedded FPGA platform. First, with the guidance of a well-trained teacher network, a high-performance student model is trained through feature-level knowledge distillation. Despite containing only 2.68 KB of parameters, the student model achieves competitive diagnostic performance. Furthermore, we designed generic IP cores for the convolutional, pooling, and fully connected layers, which can flexibly accommodate various network architectures and facilitate parameter adjustments. This design significantly reduces the computational resource usage within the FPGA. Finally, experimental results on two bearing datasets demonstrate that the FPGA-deployed model achieves diagnostic accuracy exceeding 98% while maintaining a low power consumption of just 1.84 W.