FPGA Implementation of Secure Image Transmission System Using 4D and 5D Fractional-Order Memristive Chaotic Oscillators

With the rapid proliferation of real-time digital communication, particularly in multimedia applications, securing transmitted image data has become a vital concern. While chaotic systems have shown strong potential for cryptographic use, most existing approaches rely on low-dimensional, integer-order architectures, limiting their complexity and resistance to attacks. Advances in fractional calculus and memristive technologies offer new avenues for enhancing security through more complex and tunable dynamics. However, the practical deployment of high-dimensional fractional-order memristive chaotic systems in hardware remains underexplored. This study addresses this gap by presenting a secure image transmission system implemented on a field-programmable gate array (FPGA) using a universal high-dimensional memristive chaotic topology with arbitrary-order dynamics. The design leverages four- and five-dimensional hyperchaotic oscillators, analyzed through bifurcation diagrams and Lyapunov exponents. To enable efficient hardware realization, the chaotic dynamics are approximated using the explicit fractional-order Runge–Kutta (EFORK) method with the Caputo fractional derivative, implemented in VHDL. Deployed on the Xilinx Artix-7 AC701 platform, synchronized master–slave chaotic generators drive a multi-stage stream cipher. This encryption process supports both RGB and grayscale images. Evaluation shows strong cryptographic properties: correlation of −6.1081×10−5, entropy of 7.9991, NPCR of 99.9776%, UACI of 33.4154%, and a key space of 21344, confirming high security and robustness.