Observational analysis shows steep-slope switching in p-type transistors, suggesting enhanced energy efficiency.
As silicon transistors approach their scaling limits, two-dimensional (2D) materials have emerged as promising candidates for sub-10 nm devices. However, 2D p-type transistors often exhibit low on-state current and large subthreshold swing (SS) compared with the n-type counterparts, limiting the development of energy-efficient logic circuits. Here, we present that 2D SiS with a unique isolated valence band edge can be used to realize steep-slope switching and high-performance MOSFETs. As 3% biaxial tensile strain is applied to regulate the atomic configuration and suppress the orbital overlapping, a significantly narrowed isolated band appears, enhancing the energy filtering efficiency at off-state. Specially, the 2D SiS p-MOSFET achieves an ultrasteep SS of 44 mV/dec with an on-state current approaching 2000 μA/μm. This work demonstrates the great potential of 2D SiS for realizing steep-slope p-type transistors and provides a new insight on designing next-generation high-performance and low-power devices.
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Sun et al. (2025) studied this question.
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