WSe₂/SnS₂ Heterostructure Arrays with Bilateral Accumulation Contact for Scalable p-Type Transistors and Logic Circuits

Field-effect transistors (FETs) based on two-dimensional (2D) materials hold great promise as essential components in next-generation electronics. However, achieving high-performance and large-scale production of p-type 2D FETs has remained a persistent challenge. In this study, SnS2 is introduced as a tunneling contact layer, and performance-enhanced p-type WSe2 FET arrays are fabricated by utilizing a self-aligned etching strategy based on WSe2/SnS2 heterojunctions. Owing to the type-III energy band alignment between WSe2 and SnS2 forming a bilateral accumulation region at the heterojunction interface, the carrier injection is enhanced into WSe2 through SnS2 via a band-to-band tunneling process, which effectively reduces contact resistance and barrier height. The experimental results further demonstrate that, compared with normal WSe2 FETs, the bilateral accumulation contact FET (BAC-FET) exhibits notable improvements in mobility, on-state current, and on/off ratio. Additionally, various logic circuits, including inverter, NOR, NAND, OR, and AND gates, are realized based on the BAC-FET arrays.