Design and Fault Analysis of a Triple Modular Redundant ALU for Radiation-Tolerant FPGA Applications

In this paper, we present the design and fault analysis of a radiation-tolerant Arithmetic Logic Unit (ALU) using Triple Modular Redundancy (TMR) implemented on FPGA using SystemVerilog. Radiation-induced faults, particularly Single Event Upsets (SEUs), pose a significant risk to reliable digital system operation in space and nuclear environments. To address this, we propose a fault-resilient 8-bit ALU architecture integrating TMR and a parameterized fault injection mechanism. Additionally, a partial TMR scheme and various majority voter designs are evaluated to balance resource utilization with fault tolerance. The simulation was conducted using EPWave, and results demonstrate the proposed design's capability to maintain correct operation in the presence of injected faults, validating its reliability and robustness.