This work demonstrates nanoscale josephson junctions enhance superconducting memory performance, suggesting efficiency improvements in device design.
Superconducting flux memory devices fabricated with nanoscale junctions and high-inductance materials can maintain high-speed access performance while significantly reducing the area required for superconducting loops. In this work, we present a method for preparing nanoscale NbN-based superconductor/normal-metal/superconductor (SNS) Josephson junctions that combines electron beam lithography with chemical mechanical planarization process. Scanning electron microscope images reveal that the junction has a very round shape, while cross-sectional transmission electron microscopy shows that it is a truncated cone structure, characterized by a narrow top and a wide bottom. The minimum barrier diameter of the junction is 51 nm, with the diameter at the interface between the wiring layer and the top electrode being just 27 nm. These nanoscale junctions exhibit excellent Josephson properties with critical current density Jc of 673 ± 64 kA/cm2 and characteristic voltage Vc of 1.63 ± 0.45 mV at 4.2 K. Furthermore, we designed the superconducting memory cell based on the simulated inductance values of the NbN loop and the nanoscale NbN-based SNS junctions. The cell has a total area of 12.6 μm × 6.5 μm, and contains a RF-SQUID with one junction in the storage loop and a DC-SQUID with two junctions in the readout loop. Using the flux-locked and feedback measurement method, a clear flux hysteresis curve can be obtained to verify the read-write functions of the device.
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Zheng et al. (2025) studied this question.
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