Analysis of Negative-Capacitance (NC) FET: A Device to Digital Circuit Level Implementation for Low power applications

This paper highlights the significant impact of ferroelectric (FE) layer thickness (tfe) on both Negative Capacitance (NC) FET devices and their circuit performance. The analysis is conducted using fully calibrated Sentaurus TCAD simulations for a 30 nm FDSOI technology node, examining how tfe affects the figures of merit for n-type and p-type devices, as well as the voltage transfer characteristics (VTC) and noise margins (NM) of inverter circuits. Initially, we assess the electrical parameters of the devices, such as ION, subthreshold slope (SS), ION/IOFF ratio, and gate capacitance (Cgg), by varying tfe up to the point where hysteresis in the I-V characteristics begins. We then investigate the adverse effects of Negative Differential Resistance (NDR) caused by drain-to-gate coupling, which imposes additional constraints on the maximum allowable tfe. Circuit analysis is performed using the Cadence Virtuoso tool, employing a look-up table-based Verilog-A model. Calculated value of propagation delay, VTC and NM for both device types and designed inverter with presumed NC-FET improves average propagation delay by 15.38% compared to inverter with base line FET. Overall, the NC-FET inverter design demonstrates superior performance metrics in terms of average propagation delay (τP) when compared to the baseline complementary FET inverter.