Design Optimization of Spacer Engineered Junctionless-FishBone (JL-FB) FET at 5 nm Technology Node: Device to Circuit Level Implementation

Fish-Bone (FB) FETs are emerging as strong contenders for sub-5 nm technology nodes due to their simplified fabrication and CMOS compatibility. This work introduces the first Junctionless FB FET (JL-FB FET) design optimized at the 3 nm node using spacer engineering. Compared to FinFET, Nanowire, and Nanosheet FETs, the proposed JL-FB FET achieves up to 57.5%, 57.47%, and 94.07% improvements in ION, along with 99.98% reduction in IOFF and 99.95% enhancement in ION/IOFF over Nanosheet FETs. Spacer engineering with single-k and dual-k dielectrics further improves device characteristics. Replacing Air (k = 1) with TiO₂ (k = 39) yields a ~5× improvement in ION/IOFF, ~2 mV/dec reduction in SS, and 3.6 mV/V reduction in DIBL. Dual-k spacers such as SiO₂+TiO₂ enhance analog metrics, while Air+HfO₂ boosts RF performance. CMOS inverter simulations reveal improved noise margins (NML: 310.67 mV, NMH: 321.96 mV) and gain with dual-k configurations. These findings suggest that the optimized JL-FB FET is a promising candidate for ultra-scaled low-power DC, analog, and RF applications in future CMOS technologies.