Analysis reveals enhanced charge transport and reduced hysteresis in perovskite transistors, implying crystallization significantly affects performance.
One of the main obstacles in achieving a reliable operation of perovskite transistors at room temperature is severe ion migration, which can screen the applied gate field, resulting in poor field-effect behavior and large dual-sweeping hysteresis. To reduce ionic defects a major challenge is to manage the crystallization process to achieve high-quality films. We have investigated the correlation between crystallization, thin film morphology, molecular orientation, charge transport properties, as well as the device performance of two-dimensional tin halide perovskite field-effect transistors (FETs). FET operation parameters, including mobility, threshold voltage, hysteresis, and subthreshold swing improved drastically with larger grain size, indicating that grain boundaries can be viewed as trap centers for charge carrier transport and pathway for ion migration. Therefore, reducing the number of grain boundaries is a prerequisite to increase FET performance. We demonstrate that subtle changes in the molecular structure and processing conditions have a significant impact on the molecular conformation, film morphology, as well as the charge carrier transport in perovskite films.
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Blom et al. (2025) studied this question.
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