Fabrication and Analysis of Metal-Oxide-Semiconductor Capacitors: Investigating C-V Characteristics for Varying Pad Sizes

Abstract The main objective of the experiment is to fabricate Metal-Oxide-Semiconductor Capacitors (MOSCAP) using techniques like physical vapor deposition (PVD), photolithography, and etching, and to analyze the Capacitance-Voltage (C-V) characteristics. By comparing the measured C-V behavior of MOSCAPs with varying pad sizes to the theoretical predictions, the students would learn how the important fabrication parameters and pad sizes affect the device performances. The wafers were oxidized beforehand. Upon cleaning the oxidized wafers, PVD was performed. The wafers were loaded into a thermal evaporator, and Aluminum was deposited on it. After surface preparation, a spin coater was used, and then the hot plate for baking at 120ºC. Through photolithography, precise patterning was done. Metal etching was done at 40ºC. Buffered oxide etch was used to remove oxide and the resist was stripped off. The data for C-V characteristics were collected at the probe station. The results were then presented in two graphs plotted using Excel. The graphs showed results as predicted. The capacitance is always higher for the one with the larger pad compared to the one with the smaller pad. The graphs also shifted to right possibly due to interface traps, fixed charges, or work function mismatches.