Investigation of the impact of gate oxide thickness variation of Junction-less FinFET using BSIM-CMG model for LIF neuron and STDP circuit application

In neuromorphic circuits, Leaky Integrate-and-Fire (LIF) neuron and Spike-Timing-Dependent Plasticity (STDP) circuits are very much essential. These circuits are significantly influenced by the characteristics of the transistors used in their design. In this work, the impact of gate oxide thickness variation on the performance of FinFET-based neuromorphic circuits using the (Berkeley Short-channel IGFET Model—Common Multi-Gate) BSIM-CMG model is investigated. TCAD simulations are carried out to analyze the electrical haracteristics of FinFETs with varying oxide thicknesses. The circuit-level simulations are carried out using Cadence tool to evaluate their impact on synaptic weight updates in STDP and LIF neuron operation and circuits. The results show that reducing the gate oxide thickness from 5 nm to 2 nm enhances the capacitor voltage response, thereby improving charge storage and synaptic weight modulation. It has been shown that there is a consistent increase in capacitor voltage as oxide thickness decreases, which directly impacts the learning efficiency of STDP circuits. Varying oxide thickness will also impact on firing frequency of LIF neuron circuit. These results signifies performances of STDP and LIF neuron circuits for neuromorphic applications.