An Area Efficient Approach to Realize Vedic Multiplier using 4–2 Compressor adder for Image processing Applications

A 4–2 compressor adder has been proposed to obtain an area- and power-efficient vedic multiplier for image processing applications. Vedic multipliers generate parallel partial products by eliminating unnecessary stages using the Urdhva Tiryakbhyam approach for reducing hardware area. A digital cadence Innovus implementation tool that uses 45 nm process technology has been employed for the proposed vedic multiplier derived from the compressor adder design. The synthesis results reveal an 18.4% reduced hardware area and a 14.1% saving in power usage. The effectiveness of the multiplier has been examined in various image processing applications. The recommended multiplier architecture, in contrast to the exact output image, on average, processes images with the highest Mean Structural Similarity Index Metric (MSSIM) having 92% structural similarities. The multiplier produces the highest value of the Figure of Merit (FOM), indicating a good balance between energy efficiency and accuracy.