The FinFET to Nanosheet Transition: A Critical Enabler for Energy-Efficient AIoT Applications

Abstract The relentless scaling of complementary metal-oxide-semiconductor (CMOS) technology, as dictated by Moore's Law, has driven the semiconductor industry through multiple transistor architecture revolutions. The planar bulk MOSFET, after decades of dominance, was succeeded by the three-dimensional FinFET at the 22/16 nm node to overcome severe short-channel effects (SCEs). However, as scaling continues to the 5 nm node and beyond, the limitations of the FinFET have become apparent. This literature review examines the journey from FinFETs to the next-generation architecture: the Gate-All-Around (GAA) Nanosheet Field-Effect Transistor (NSFET). It covers the motivations for this transition, the advantages and challenges of nanosheet technology, and the future roadmap towards forksheet and complementary FET (CFET) architectures. This paper presents a comparative analysis of power and delay characteristics between 5nm FinFET and 3nm Gate All Around (GAA) Nanosheet technologies using the educational EDA tool. A standard CMOS inverter is used as a test vehicle for this analysis. Simulation results demonstrate a significant improvement in the power-delay product (PDP) for the 3nm Nanosheet technology, improvement in propagation delay compared to the 5nm FinFET, primarily due to superior electrostatic control enabling lower supply voltage operation. The findings underscore the critical importance of the transition to GAA architectures for next-generation applications in Artificial Intelligence (AI), Machine Learning (ML), and the Internet of Things (IoT), where computational efficiency and ultra-low power consumption are paramount.