We have evaluated the feasibility of selectively etching, with gaseous HCl, high versus low Ge content SiGe layers. To that end, we have grown {20 to 25 nm thick Si / ~ 12-15 nm thick Si 0.8 Ge 0.2 or Si 0.75 Ge 0.25 / ~ 11-14 nm thick Si 0.5 Ge 0.5 } multilayers on SOI substrates. After a low temperature capping with SiN, such stacks were patterned into regular arrays of square mesas or lines with a stop on the buried oxide, to laterally etch the layers of interest. We first determined, at 500°C, 600 Torr, the (001) blanket HCl etch rates of SiGe 30% and 40%: 1.4 and 5.3 nm min. -1 . We then switched over to patterned wafers. The lateral selective etching of Si 0.5 Ge 0.5 versus Si 0.8 Ge 0.2 (and Si) was feasible and the following features highlighted: (i) Si 0.5 Ge 0.5 lateral etch rates along the <110> directions were much smaller than in the vertical [001] direction and (ii) because of micro-loading, lateral etch rates were definitely higher for squares than for lines (0.9-1.1 nm min. -1 for lines, to be compared with 1.7–2.1 nm min. -1 for squares). Meanwhile, the lateral selective etching of Si 0.5 Ge 0.5 versus Si 0.75 Ge 0.25 was far from being perfect, with much higher Si 0.5 Ge 0.5 etch rates and a significant Si 0.75 Ge 0.25 recessing at tunnel entrances. Si 0.75 Ge 0.25 floors and ceilings were otherwise far more etched and thus tilted than Si 0.8 Ge 0.2 ones. Inserting very thin Si spacers between Si 0.5 Ge 0.5 cores and Si 0.75 Ge 0.25 claddings partly solved those issues, with no recessing and lesser etchings at the entry points of tunnels.
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Hartmann et al. (2024) studied this question.
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