Trap resistance triggers SCR with low capacitance

In this paper, an ESD protection device for high-speed I/O interface circuits is proposed, and an SCR protection device utilizing trap resistance triggering and reduced parasitic capacitance is designed and investigated, and verified in a 0.18 μm CMOS process. The design has a low overshoot voltage under ESD stress, a high failure current, a sufficiently low parasitic capacitance, and a low leakage current, and is therefore suitable for low-voltage ESD protection for high-speed circuits in CMOS processes.