Gate Resistance Integration in SiC MOSFETs: Performance Simulations under Different Implementation Methods

This paper proposes performance evaluation of SiC MOSFETs power devices introducing in the device layout some specific design to achieve desired value of intrinsic gate resistance. This aspect can be helpful to eliminate external components such as gate resistance, saving space and cost, considering the application of the gate driver directly connected to the power device. Description about the layout modification of the device die is presented and dedicated simulation approach is set and exploited to predict the signal propagation on the die while verifying the gate resistance defined by the new layout structure. Experimental results including switching losses evaluations performed with double pulse tests sequence with half-bridge converter realized with new SiC MOSFETs devices, are also reported in the paper.