Gate Switching Lifetime of P-Gate GaN HEMT: Circuit Characterization and Generalized Model

In converter operations, a major reliability concern of the GaN high electron mobility transistor (HEMT) with a p-GaN gate (i.e., p-gate GaN HEMT) is the very small gate overvoltage margin. Despite many reliability studies using dc bias and pulse I – V test, the gate reliability under the application-use condition has been seldom reported for p-gate GaN HEMTs. Meanwhile, due to the unique electrostatics of the p-GaN gate, the applicability of the conventional dc lifetime model to p-gate GaN HEMTs is questionable. To address these gaps, this article develops a new circuit method to produce the application-like gate voltage ( V G ) stress that consists of a resonant ringing added to an operational dc bias. Using this circuit method, the gate lifetime of commercial p-gate GaN HEMTs is characterized under multiple variables, including the dc bias, peak ringing V G ( V G(PK) ), ringing pulsewidth (PW), switching frequency ( f SW ), and temperature ( T ). The lifetime is found to show complex relations with V G(PK) , PW, and f SW and a positive temperature dependence. Based on the statistical data, a gate-switching lifetime model is constructed for the first time for p-gate GaN HEMTs. This model comprises the V G -, f SW -, and T -related acceleration functions and allows one to determine overvoltage stress from an arbitrary V G waveform and further calculate the gate lifetime. The gate reliability is revealed to be an increasingly significant concern under high f SW , low T , and increased parasitics in the driver loop. The new characterization circuit and switching lifetime model underscore the importance of application-based reliability methodology. The characterization results suggest the need for performing gate qualification for p-gate GaN HEMTs under high- f SW , low- T switching conditions.