Design of a high-speed 7.2 Gbps/lane receiver for MIPI D-PHY interface utilizing 18 nm FinFET technology

This study presents an advanced design for a high-speed receiver tailored for the MIPI D-PHY Interface, capable of handling data rates up to 7.2 Gbps per lane. The design is developed using 18 nm fin field-effect transistor (FinFET) technology and is rigorously simulated under varying process, voltage, and temperature conditions (PVTs) to ensure robustness. The architecture of the receiver integrates several key components: differential pair sensing, a folded cascode continuous time linear equalization (CTLE), a single-ended operational amplifier, and a cross-coupled stage. Operating at a supply voltage of 0.72 V in the worst-case scenario, our CTLE achieves a peaking gain of 17.77 dB at 4.26 GHz. The design demonstrates a maximum jitter of 19.63 ps at an offset voltage of ±2 mV. Notably, the power efficiency of our receiver is optimized to 0.85 mW/Gb/s, totaling 6.1 mW, with dual supply voltages of 1.98 and 0.88 V. This work contributes to the field by offering a highly efficient solution for fast data transmission with reduced power consumption and enhanced signal integrity.