Design of a high-precision time-to-digital converter in an Elitestek Ti60 field-programmable-gate-array

The time-to-digital converter (TDC) implemented in a field-programmable-gate-array has garnered widespread attention due to its flexibility and high-performance capabilities. However, issues such as non-uniformity, the bubble in the tapped delay line, and the presence of certain ultra-wide delay units can significantly compromise the precision and nonlinearity of the TDC. In this paper, we propose a high-precision TDC in an Elitestek Ti60 FPGA, effectively eliminating the adverse effects of non-uniformity, the bubble, and certain ultra-wide delay units. The TDC is constructed with a 318-stage delay chain and operates at a low system clock frequency of 150 MHz. The least significant bit (LSB) of the TDC is 21.92 ps. The differential nonlinearity (DNL) is between (−0.976, 1.615) LSB and the integral nonlinearity (INL) is between (−1.446, 2.678) LSB. The TDC achieves a root-mean-square error of 14.783 ps when utilized for measuring various time intervals.