Design and Implementation of Energy Efficient Area Optimized High Speed Approximate Multipliers Using Higher-Order Compressors

Multipliers play an important role in Digital Signal Processing (DSP) applications, but their traditional design has significant limitations, such as high power consumption, huge area requirements, and long critical path delays. While inexact multipliers have emerged as a potential solution, they are best suited to applications where a small variation from absolute accuracy is acceptable. These inexact multipliers provide significant power savings and reduced area requirements while retaining acceptable levels of precision. Approximation is introduced at both the compressor and multiplier levels, resulting in significant reductions in area and power use. This study proposes an efficient approach to multiplier design that uses higherorder compressors rather than standard 4:2 compressors. The aim is to optimize hardware usage and power consumption. We propose five types of approximate compressors (4:2, 5:2, 6:2, 7:2, and 8:2) and develop four versions of the 8X8 approximate multiplier. These versions use approximation at various points of partial products with either exact full adders or Carry Skip Adders (CSKA) to improve efficiency when adding partial products at the end. Our innovations, which include two stages of partial product integration, result in significant reductions in power and hardware consumption, with average power savings of 62% and hardware reductions of up to 48%. The article also includes a thorough comparison of power, area, latency, and error analysis, emphasizing advances in hardware efficiency.