Energy-Efficient Approximate Multiplier Architecture Using 4-2 Approximate Compressor for Image Processing Applications

Approximate computing plays a significant role in the design of energy-efficient architectures for error-tolerant systems. This paper proposes a 4-2 approximate compressor using an improved design of a 3-2 approximate compressor with the help of AND-OR recoding. An architecture of the approximate Dadda multiplier is presented using the proposed 4-2 approximate compressor. Synthesis results show improvements in terms of power delay product (PDP), energy-delay product (EDP), and area delay product (ADP) as compared to the exact multiplier as well as the existing approximate multipliers. The proposed approximate multiplier achieves significant reductions in PDP, EDP, and ADP compared to exact multipliers, with decreases of 61%, 71%, and 64%, respectively. The real-life application of the proposed approximate multiplier is illustrated with the help of image blending and smoothing. The efficacy of the proposed multiplier is validated via the Figure of merit (FOM) and it is found that the proposed multiplier provides better results than the previously reported approximate multipliers.