Low-Power and High-SFDR Current Steering DAC Design in 65-nm CMOS Using C-DEM Method

Wireless Sensor Networks (WSNs) with low power consumption are getting more and more important. This work introduces an innovative low-power Digital-to-Analog Converters (DACs) architecture designed specifically for operating lowpower WSNs. The emphasis is placed on the essential role of DACs within WSNs, acknowledging their significant power consumption. This study presents a Compact Dynamic Element Matching (C-DEM) method, aiming to mitigate the power and area redundancies associated with conventional DEM techniques and to achieve power and area efficiency through the implementation of C-DEM. Dynamic element matching stands out as a widely recognized technique employed in the design of high-performance DACs. The present research was motivated by the noteworthy finding that DAC input data typically displays appropriate randomness. As an alternative to the traditional reliance on a Pseudo Random Number Generator (PRNG) in usual DEM approaches, this feature allows using the input data itself for random selection of current sources. When the PRNG is removed from a DAC and input data is used instead, the DAC's space and power consumption are significantly reduced while still providing the performance requirements of low-power WSNs. This is brought on by the PRNG's high power requirements and substantial DAC footprint. In comparison to a DAC employing the traditional DEM, the C-DEM-based DAC consumes less power and area reduction. In the proposed C-DEM, when DAC uses a traditional DEM, the Spurious-Free Dynamic Range (SFDR) is not as good.