⌘+K

Pulse Explore Communities Researchers Journals

Home Communities Explore

June 12, 2024Open Access

Hypervisor Extension for a RISC-V Processor

Jaume Gauchola JuanJosé Costa Enric Morancho Ramón Canal Xavier Carril Max Doblas Beatriz Otero Alex Pajuelo Eva Rodríguez Javier Salamero Javier Verdú

View Full Paper

Ask AI

Bookmark

Share

Abstract

This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one.

Discussion

No takes yet. Share an insight, caveat, or question.

Cite This Study

Gauchola et al. (2024) studied this question.

synapsesocial.com/papers/68e651cbb6db6435875e295b https://doi.org/10.48550/arxiv.2406.17796

View Full Paper

Ask AI

Bookmark

Share

Keep reading

Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context:

1Count overflow and privilege mode filtering extension implementation on a RISC-V on-board processor2024 · 2 citations
2Implementation of RISC-V ProcessorOriginal Research · 2025
3Exploring Instruction Set Extension Emulation for Long-Term Support of RISC-V ProcessorsOriginal Research · 2026
4Design and implementation of a single-cycle RISC-V microcontroller with custom ISA extensions and peripheral integrationOriginal Research · 2026
5Design of RISC-V processor for accelerator power controller2024

More related papers

Synchronization Support in 64-bit Out-Of-Order Superscalar Dual-Core RISC-V Processor2024
Optimal Design for High Performance Computing Systems Based on 5-Stage Pipeline 32-bit RISC-V Processor2025
Taking on RISC for Energy-Efﬁcient Computing in HEP2025